FIFO:How to slow down the clock Frequency from 50 Mhz

Hello,

50 Mhz is the clock speed used by the CPU to process assembler instructions.

Instructions can require multiple clock pulses, this depends also on the cpu type.

​You are looking at a way to slow down the loop:

#include <stdio.h>
#include <unistd.h>
int main()
{
	while (1)
	{
	  printf("Hello from Nios II! \n");
	  usleep(1000000);
	}
  return 0;
}

Best Regards,

Johi.

I have added "usleep(1000000)" but printing speed is slow but i am getting correct answer.

Can u check my FIFO design.

​I think the best way to control the flow of counter instead of slowing down the whole system. Probably you use the almost full signal from the FIFO to stop or disable the write signal from the counter. Currently ,the module "block count" always receive data from counter regardless of any condition. Hope this helping you.

Thanks for your response.

I am new to the altera.

>>Probably you use the almost full signal from the FIFO to stop or disable the write signal from the counter.

How it can done , can you explain me briefly.

Thank you

It's harder in explanation ​if you design it in schematic. I make it simpler here:

1) Invert almost full signal from FIFO

2) "ANDed" it with the enable of counter

3) Drive output of "ANDed" signal to both of write FIFO and enable of counter. This is to halt the transfer completely.

Did you mean to create own FIFO IP ?

1) Invert almost full signal from FIFO

2) "ANDed" it with the enable of counter

3) Drive output of "ANDed" signal to both of write FIFO and enable of counter. This is to halt the transfer completely.

Sorry to ask silly questions. In NIOS, i need to do ??

The method does not involve any NIOS software or C coding. It is done through logic level. You have to modify the circuitry in the schematic and use primitive logic to construct.

Here's an example ftp://ftp.altera.com/up/pub/Tutorials/DE2/Digital_Logic/tut_quartus_intro_schem.pdf

Really sorry, i am not able to understand your logic level flow. can you explain in a better way like schematic diagram.

I need your help to complete this process. But Finally, i need to communicate with NIOS. Because through WIZNET i need to communicate with PC.

Thanks

But Finally, i need to communicate with NIOS. Is it possible with designs building with primitive logic diagrams ? ?