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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

FIFO Outputs all HiZ in RTL Simulation

Hi All, I am still a beginner to FPGAs, but I think I'm making good progress. I am able to simulate my own Verilog code in ModelSim-Altera and everything looks correct. However, when I tr...
DNguy4's avatar
DNguy4
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Hi,

I have very similar problem but I can't fix it yet. I see "U" on all outputs of my Fifo_x16. I generate the Fifo_x16 using Quartus Pro 18.1 and I use VHDL 2008. I think vsim doesn't use the right library for the simulation. Can you please tell me how to make it use the right library. I think Fifo_x16 is not part of the megafunction (mf).

Thanks