Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

FIFO Outputs all HiZ in RTL Simulation

Hi All, I am still a beginner to FPGAs, but I think I'm making good progress. I am able to simulate my own Verilog code in ModelSim-Altera and everything looks correct. However, when I tr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Gah! Of course it is.

Thanks for all your help. It's working now!

For future people: You have to also make sure you add the library to your modelsim.ini file in the project directory. My library section looks like this:

[Library]

others = $MODEL_TECH/../modelsim.ini

; Altera Primitive libraries

;

; VHDL Section

;

;

; Verilog Section

;

altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf