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Altera_Forum
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10 years ago

FIFO Outputs all HiZ in RTL Simulation

Hi All, I am still a beginner to FPGAs, but I think I'm making good progress. I am able to simulate my own Verilog code in ModelSim-Altera and everything looks correct. However, when I tr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I have removed it from the project. What do I need to do besides add the "-L altera_mf" to my vsim command? I thought ModelSim-Altera came with all the Altera libraries already installed. I see a huge list in the libraries pane, and altera_mf is definitely in there.