Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorFIFO Outputs all HiZ in RTL Simulation
Hi All, I am still a beginner to FPGAs, but I think I'm making good progress. I am able to simulate my own Verilog code in ModelSim-Altera and everything looks correct. However, when I tr...
Altera_ForumHonored Contributor
Honored ContributorThat implies it is using the sync_fifo_bb file as the reference for the sync_fifo - hence the Z outputs. It also now means you havent included the altera libraries properly.
Remove the _bb file from the project. This is only for copy/pasting into your code.
