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Altera_Forum
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10 years ago

FIFO Outputs all HiZ in RTL Simulation

Hi All, I am still a beginner to FPGAs, but I think I'm making good progress. I am able to simulate my own Verilog code in ModelSim-Altera and everything looks correct. However, when I tr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

That implies it is using the sync_fifo_bb file as the reference for the sync_fifo - hence the Z outputs. It also now means you havent included the altera libraries properly.

Remove the _bb file from the project. This is only for copy/pasting into your code.