Altera_Forum
Honored Contributor
14 years agofifo megafunction simulation problem
hi there,
i'm new in fpga world and i just started playing with megafunctions, and already encountered problems. i'm trying to adapt a working structure on xilinx to altera(the project isn't mine, i just have to adapt it to altera, so i can learn more about this job). i'm using a module with different clocks for read and write, asynchronous reset, and only the rdempty signal. when i simulate the entire module, after inserting some data's, i try to read them, but the "q" signal is zzzzz :( i also noticed that the rdempty signal is in a hi-z state. i replaced the megafunction fifo with a manual made module, having the same properties(different clocks, rdempty signal) and it works properly. Any ideas? please