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Altera_Forum
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11 years ago

FIFO IP Full and Empty Simultaneously

Hello, I have DC FIFO I am working with in my design, and the FIFO is constantly showing it is both full and empty at the same time. The FIFO fills up with sampled and analyzed data from an AD...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Has this issue been in any way resolved, or is there a workaround? I am experiencing the same problem, but deleting db and resynthesizing does not help at all. I have tried to circumvent using the empty and full signals and just use the usedw signal, but it doesn't show the right values either(It shows 0 when it should show 10 or such).

No parts of my design fail timing.