FIFO IP Full and Empty Simultaneously

I have a similar problem with the LPM_FIFO...the fifo is 4 words deep, single clock, and thus has two usedw bits. If the usedw is anything but zero, I read the data from the FIFO, and several microseconds later, check to see if there is any more data. Typically usedw reads 1, and no more data has been pushed to the FIFO, but for some strange reason, it still reads 1. If I read the fifo again, usedw then decrements to 0. And the data that I read out this second read is the data which was pushed 3 times earlier. And this happens cyclically...4 times usedw does not decrement to 0 on the first read, then 1 time it decrements to 0 properly.

That is, it is acting as if there is are internal pointers to a circular queue which determine where to push and pop the data, and the usedw decrement to zero properly only if the queue index is 0.

It is an old design that worked fine for years, originally compiled with Quartus 9, with a MAX II EPLD. Perhaps this is a feature introduced in Quartus 13?

Since it might be device dependent, I can add that now the device is a MAX V EPLD.

Perhaps someone from Altera can check this out? It would be any easy mistake to make in doing the usedw logic, and while I understand that the LPM_FIFO is and old and fully debugged design, it is conceivable that someone tried to fix or optimize it for new silicon and made an error.

Is there a way to see the logic at the gate level? Even in these days of "intellectual property" craziness, it is hard to see that anyone could see anything proprietary about a simple FIFO.http://www.alteraforum.com/forum//images/icons/icon7.png