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Altera_Forum's avatar
Altera_Forum
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13 years ago

FIFO holding one item in it

Gentlemen;

I have used the Megafunction wizard to create a 8x64 FIFO buffer on my DE0-NANO board. It is to buffer signals received on GPIO0[0] at 9600 baud and retransmit them on GPIO1[0]. I have written the routines in Verilog and all is working well with one exception. The first time I send a series of characters , a hex 00 is retransmitted followed by all the characters received except the final one. The next string I receive, the retransmitted string starts out with the final character in the previous string and again does not retransmit the final character in the current received string.

I suspect that I may have a coding issue, but for the life of me I cannot figure it out. Is there some trick to using FIFO buffers that I may be missing?

I have attached the 4 small Verilog files that form the system.

I read a new character from the FIFO buffer if it is not empty and the transmitter is not busy.

I display the usedw_sig on LEDs [5:0], the Busy signal from the transmitter to LED[6], and the empty_sig to LED[7]. These seem correct except the the FIFO empty signal is on before the final character is sent back out. I have been working on this for quite some time and my frustration level is getting quite high.:cry:

Many thanks for any assistance that someone might choose to offer.

Regards,

Geof

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    In the default configuration for FIFO's you have to do a read request on the read side and one clock cycle later the first data is presented on the output. This is why you read 0x00 on your first read.

    You can configure the FIFO in "read ahead" mode to avoid this or adapt your logic according to the one clock cycle delayed read.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    In the default configuration for FIFO's you have to do a read request on the read side and one clock cycle later the first data is presented on the output. This is why you read 0x00 on your first read.

    You can configure the FIFO in "read ahead" mode the avoid this or adapt your logic according to the one clock cycle delayed read.

    --- Quote End ---

    Thank you, schmalisch,

    That was 100% correct and solved my problem. :) I really appreciate you taking the time to respond to my request.

    Kind regards,

    Geof