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Altera_Forum
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11 years ago

FIFO configuration in Qsys to make the "full" signal visible to HPS.

Hi everyone,

I now have a question in Qsys configuration for FIFO in order to make the status signal "full" visible to the HPS, then the software.

See in qsys, the "full" coming out from the traditional FIFO module and is an output of avalon_slave_0, the same as 32-bit q from FIFO (see attached). Previously I use ioread32() in software testbench to read the data from FPGA, and the signal type of 32-bit-output data is "readdata". Now I want to make the software could also use the ioread() to read the "full" signal to check the FIFO status, however the signal type for the "full" could no longer be "readdata". But I'm not sure what signal type it should be so that I could still use the ioread() or other read functions in software to read the signals.

Any ideas? Thanks in advance.

http://www.alteraforum.com/forum/attachment.php?attachmentid=9500&stc=1

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Moving this out of the SoC forum. The problem you are running into is that Avalon-MM 2.0 requires that readdata or writedata to be a multiple of the symbol (byte) size of 8 bits. I recommend padding your used signal to be 16-bit or 32-bit so that you can integrate it into Qsys.