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Altera_Forum's avatar
Altera_Forum
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11 years ago

FIFO configuration in Qsys to make the "full" signal visible to HPS.

Hi everyone, I now have a question in Qsys configuration for FIFO in order to make the status signal "full" visible to the HPS, then the software. See in qsys, the "full" coming out from ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Moving this out of the SoC forum. The problem you are running into is that Avalon-MM 2.0 requires that readdata or writedata to be a multiple of the symbol (byte) size of 8 bits. I recommend padding your used signal to be 16-bit or 32-bit so that you can integrate it into Qsys.