FIFO based on DDR

I started looking into this a few years ago (application required full memory bandwidth at DDR), and I came to the conclusion that it likely would not be possible, due to the extra overhead associated with interfacing DDR parts. In your case, you would have to determine what sort of requirements you have, and then take a look at the actual memory bandwidth of a DDR interface, and make that decision. At the time, I found that Altera's documentation was pretty nebulous with respect to performance (for their supplied DDR interface logic). That might have changed, so I don't know. I was hoping that they would have some sort of equation stating mem_bandwidth = f(ratio_writes, ratio_reads, clock_rate), or something to that effect. Instead, there were 3-4 example designs, with what appeared to be the empirically-determined efficiency.

In my case, we had put a DDR memory on the board for the purpose of a delay FIFO (start writing, t_delay, start reading => delays data for duration of t_delay, indefinitely). I needed to run at 2x clock rate (which is why we went with DDR), but then found out, after the fact, that the memory bandwidth was really only 60% or so of 2x clock rate. So, we went about it a different way.

You might have a lot better luck if your application is something like a rate-adapter with a burst on one side and constant reading @ rate on the other. Hope this helps.