Fibonacci Code

module fibclk(

input clk,

input reset_n,

output [7:0] LED

);

reg [7:0] prev;

reg [7:0] actual;

assign LED = actual;

always @(posedge clk or reset_n)

begin

if(!reset_n)

begin

prev = 8'd0;

actual = 8'd1;

end else

begin

prev = actual;

actual = actual + prev;

end

end

endmodule

MAKE ATTENTION :

1) no edge on more than one signal in alway key (only the clock signal) !!!!!

2) <= is comparator in VERILOG but assignment in VHDL, you are in VERILOG so it is = affectation.

I don't understande your problem on the LED !!!

To see some think, you must use very low frequency clock, if not, you will see all LEDs ON !!!!

You need to reduice the Frequency of the primary clock ( 0.5Hz is very good to see binary number of fabonacci). I prefer using 7seg dusplay.

Good luck

Impossible to contact you because my reply counter is too low (must be 10 to be able to send PM)