The module is completely asynchronous. You really need a clock and hopefully a reset.
try this:
module fib(
input clk,
input reset_n,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5,
output LED6,
output LED7,
output LED8
);
reg prev;
reg actual;
assign LED1 = {7'd0,actual};
assign LED2 = {7'd0,actual};
assign LED3 = {7'd0,actual};
assign LED4 = {7'd0,actual};
assign LED5 = {7'd0,actual};
assign LED6 = {7'd0,actual};
assign LED7 = {7'd0,actual};
assign LED8 = {7'd0,actual};
always @(posedge clk or negedge reset_n) begin
if(!reset_n) begin
prev <= 8'd0;
actual <= 8'd1;
end else begin
prev <= actual;
actual <= actual + prev;
end
endmodule