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Altera_Forum's avatar
Altera_Forum
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18 years ago

Few simulation problems with Quartus II 7.1 SP1

I have two problems with simulation in QUARTUS II software. Firstly, i have problem with simulation time. I can set maximum simulation time to 1 us. How can I change it to simulate my design in longer time period ( for example 1 ms) ? I am using free Web Edidtion of Quartus software.

Secondly, I have tried to simulate FFT IPcore (from IPmegacore library) and somehow I couldn't obtain any simulation results (basically, simulation wasn't working). How can I deal with this problem ?

Thank You for Your interest.

Best regards.

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    When you have your .vwf file open, go to Edit -> End Time. How long the simulator runs and how long your simulation input file is are two different things. (Makes more sense in the reverse, where you might have a really long input .vwf, but only want to run the simulator for a portion of that time.

    The second part needs more info/debugging. Just saying the simulation wasn't working doesn't help a lot. Are you not getting outputs(something wrong with the setup), or do you get output transitions, just not what you expect, and think it's functionally incorrect?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    You're right. In FFT simulation output is undefined (X) . I don't know why. Simulation shows warning that come outputs can not be shown, cause registers have been synthesized away. But all inputs and outputs are used in design.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    That's usually do to not driving one of the inputs. For example, if you don't drive the reset line, then the simulation doesn't know what the register is doing, and all the registers become unkown, 'X'. It doesn't have to be a global signal like the reset though. If any input is undriven, then the registers it drives become unkown, and that can quickly propogate unkown values through all the registers in the design.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hmmm... I drive reset signal, but I realized that reset can be active high, not low ;) So how is with reset signal in this IPcore ?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Driving the reset signal to the wrong value would not cause the outputs to go unkown(X), it would just cause them to reset. (The documentation should state what the reset is, but unless the name has an _n, or rstn, or something like that to indicate a negative polarity, I believe the general assumption is that it will be positive logic, i.e. 1 will reset the device...)

    Looking at your previous post, you do get a warning that some outputs cannot be shown because registers that drive them are synthesized away. Are only some of your outputs X(which would be explained by this), or all of them(which would be explained by not driving a control signal).
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    That input port sink_valid is the one that concerns me. How come it's not being driven? I'll bet that's the issue...

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    You're right ! I didn't drive sink_valid input. Now everything is OK.