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Altera_Forum's avatar
Altera_Forum
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16 years ago

Fault tollerant state machine problems

I have been doing some experiments on using fault tollerant state machine coding schemes for use in a radiation enviroment, this means defining the state coding for the states and forcing quartus to use eser encodings.

When you do this in quartus it means that the state machine doesn't actualy get recognised as a state machine and you have to be careful over which optimisations are allowed.

However the problem I have now is for one particular encoding scheme which uses 5 bits for the state vector, quartus only actualy uses the upper four bits of the state vector, so despite me turning off optimisations it seems that quartus still manages to break my coding scheme.

My question is how can I force quartus to use exactly the state vector coding I have defined?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I know two ways:

    the first one is the use of the syn_encoding synthesis directive that is something like:

    reg [4:0] state /* synthesis syn_encoding="user" */;

    the second one is through the menu:

    settings > Analysis & Synthesis and there you can set the state encoding as "user".

    Why don't you post a project that reproduces the problem?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Well....This is a snippet of my code which contains the relevant coding bits

    architecture rtl of rad_monitor_3h is

    type state is(zero,zeroa,zerob,zeroc,zerod,zeroe,one,onea,oneb,onec,oned,onee,two,twoa,twob,twoc,twod,twoe,three,threea,threeb,threec,threed,threee,four,foura,fourb,fourc,fourd,foure,recover);

    attribute syn_encoding: string;

    attribute syn_encoding of state:type is " 00000 00001 00010 00100 01000 10000 00111 00110 00101 10010 10110 11011 11101 11100 11111 11001 10101 01101 11111 ";

    signal state1:state;

    signal next_state:state;

    signal err:std_logic;

    signal error_count,shift_data:std_logic_vector(7 downto 0);

    signal edge_shift:std_logic_vector(1 downto 0);

    signal parity_edge,slo_clk:std_logic;

    signal busy,wiggle:std_logic;

    attribute keep :boolean;

    attribute keep of state1,next_state:signal is true;

    attribute keep of shift_data,error_count:signal is true;

    attribute preserve:boolean;

    attribute preserve of rad_monitor_3h:entity is true;

    attribute preserve of rtl :architecture is true;

    Its a slightly strange state encoding becuase its based on the idea of prime states with a Hamming distance of three and companion states with a Hamming distance of one from those..... and I have used the 'user' setting in quartus but it still insists on using just four biits for the state vector.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    do you have unreachable states?

    I think that Quartus removes the unreachable states and the associated logic from the resulting FSM.

    Could this be the problem?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I think, the property "fault tolerant" needs explanation. The most basic kind of fault tolerance is to prevent locking in illegal states, but I don't see, that it's achieved by your coding scheme. Generally the Altera "safe state machine" feature should be considered.

    The shown snippet itself is inplausible, it has 31 states in the enumeration but less codings.