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Altera_Forum
Honored Contributor
15 years agoWell....This is a snippet of my code which contains the relevant coding bits
architecture rtl of rad_monitor_3h is type state is(zero,zeroa,zerob,zeroc,zerod,zeroe,one,onea,oneb,onec,oned,onee,two,twoa,twob,twoc,twod,twoe,three,threea,threeb,threec,threed,threee,four,foura,fourb,fourc,fourd,foure,recover); attribute syn_encoding: string; attribute syn_encoding of state:type is " 00000 00001 00010 00100 01000 10000 00111 00110 00101 10010 10110 11011 11101 11100 11111 11001 10101 01101 11111 "; signal state1:state; signal next_state:state; signal err:std_logic; signal error_count,shift_data:std_logic_vector(7 downto 0); signal edge_shift:std_logic_vector(1 downto 0); signal parity_edge,slo_clk:std_logic; signal busy,wiggle:std_logic; attribute keep :boolean; attribute keep of state1,next_state:signal is true; attribute keep of shift_data,error_count:signal is true; attribute preserve:boolean; attribute preserve of rad_monitor_3h:entity is true; attribute preserve of rtl :architecture is true; Its a slightly strange state encoding becuase its based on the idea of prime states with a Hamming distance of three and companion states with a Hamming distance of one from those..... and I have used the 'user' setting in quartus but it still insists on using just four biits for the state vector.