Forum Discussion
4 Replies
- Altera_Forum
Honored Contributor
You have three settings at your disposal:
FAST_INPUT_REGISTER FAST_OUTPUT_REGISTER FAST_OUTPUT_ENABLE_REGISTER For a bidirectional IO, you can set any or all of these to TRUE for the pin in question. Your design must of course actually support the function: 1 - The pin must be driven directly by a register output with no combinatorial logic. 2 - The input must be fed directly to a register with no combinatorial logic 3 - If you choose to use a fast output enable then the output enable for the pin must be driven directly by a register. Jake - Altera_Forum
Honored Contributor
--- Quote Start --- For a bidirectional IO, you can set any or all of these to TRUE for the pin in question. Your design must of course actually support the function: 1 - The pin must be driven directly by a register output with no combinatorial logic. 2 - The input must be fed directly to a register with no combinatorial logic 3 - If you choose to use a fast output enable then the output enable for the pin must be driven directly by a register. --- Quote End --- Thank you for your rapidly reply! When using a bidirection IO, the output and input are not directly fed by a register, but via a buffer. Even if my output reg before bidirection buffer is register pipelined so that there is certainly no combinatorial logic. I think course 1 and 2 are not met because of the buffer itself. Only the buffer's enable reg could be set in this condition? thank you ag~ - Altera_Forum
Honored Contributor
I should be more clear. Besides the buffer ... there can be nothing between the pin and register.
Jake - Altera_Forum
Honored Contributor
--- Quote Start --- I should be more clear. Besides the buffer ... there can be nothing between the pin and register. Jake --- Quote End --- I think I've been thinking too much to waht you've said just now, hehe~ And so according to this, I just set and apply the Fast IO register constrains directly to the Bidir IO pin, it will do work. Thank you very much!