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Altera_Forum
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16 years ago

False Path Constraints

Hi, I have two clocks coming from two different clock sources (ClkSrcA, ClkSrcB), going to two different PLLs (PLLA, PLLB), generating two clocks (ClkA, ClkB). In the design data is tran...
Altera_Forum's avatar
Altera_Forum
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16 years ago

You shouldn't set false path. Instead you should transfer data safely across clock domains. It is your responsibility, not that of TimeQuest