Forum Discussion
New ContributorFailed to create SystemVerilog interface in _hw.tcl in Platform Designer
Hi Chunxi,
Done testing. Yes, the top-level port feature that you want can be done by Pro version hw.tcl SystemVerilog interface command.
I had checked internally that this feature only be implemented starting from Pro version 17.1. That's why you'll see package require -exact qsys 17.1 in both the Standard and Pro example given https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/declaring-systemverilog-interfaces-in-hw-tcl.html and https://www.intel.com/content/www/us/en/docs/programmable/683609/22-4/declaring-systemverilog-interfaces-in-hw-tcl.html
If you check the hw.tcl generated by latest Standard version 22.1.2, you'll see it still use this package require -exact qsys 16.1. Means that Standard version not yet supports this feature and document mistake (I'll report this to internal team). Probably this feature will be supported in future Standard release.
So for now, have to stick with traditional method (SV interface used inside the RTL) for Standard version.
Thanks,
Best Regards,
Sheng
Super ContributorHi Chunxi,
SV interface in Platform Designer component top-level is supported in Standard version. Just that attributes (SYSTEMVERILOG_INTERFACE) and add_sv_interface are not supported in Standard version.
So you can still use SV interface in Platform Designer component top-level and not need to use that attributes (SYSTEMVERILOG_INTERFACE). Btw, you can go to File -> Export System as hw.tcl Component to auto-generated the hw.tcl of the component.
Thanks,
Best Regards,
Sheng
New ContributorHi Sheng,
I am using a set of RTL files to create a Platform Designer component for it to be connected with HPS in Platform Designer.
Without using add_sv_interface, SV_INTERFACE_PORT, SV_INTERFACE_PARAMETER, SYSTEMVERILOG_INTERFACE attributes in hw.tcl, how to specify systemverilog interface in hw.tcl in Quartus Prime Standard software? Are there any instructions or examples available?
Thanks,
Chunxi
