Forum Discussion
New ContributorFailed to create SystemVerilog interface in _hw.tcl in Platform Designer
Hi Chunxi,
Done testing. Yes, the top-level port feature that you want can be done by Pro version hw.tcl SystemVerilog interface command.
I had checked internally that this feature only be implemented starting from Pro version 17.1. That's why you'll see package require -exact qsys 17.1 in both the Standard and Pro example given https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/declaring-systemverilog-interfaces-in-hw-tcl.html and https://www.intel.com/content/www/us/en/docs/programmable/683609/22-4/declaring-systemverilog-interfaces-in-hw-tcl.html
If you check the hw.tcl generated by latest Standard version 22.1.2, you'll see it still use this package require -exact qsys 16.1. Means that Standard version not yet supports this feature and document mistake (I'll report this to internal team). Probably this feature will be supported in future Standard release.
So for now, have to stick with traditional method (SV interface used inside the RTL) for Standard version.
Thanks,
Best Regards,
Sheng
Super ContributorHi,
add_sv_interface and add_fileset_file <file_name>.sv SYSTEM_VERILOG PATH ../<file_name>.sv SYSTEMVERILOG_INTERFACE are attributes supported by pro version only check screenshot.
Standard version don't support those attributes check screenshot. Please use other attributes instead. Probably there're some problem with the document, I'll report this to related document team.
Thanks,
Best Regards,
Sheng
- chunxi_yu
Hi Sheng,
Thank you for the explanation.
Is my understanding correct that Quartus Prime Standard version doesn't support SV interface in Platform Designer component top-level at all?
Thanks,
Chunxi
