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Konst_777
New Contributor
New ContributorExternal Memory Interfaces Intel Cyclone 10 FPGA IP: MMR interface trouble
I checked "Enable Memory-Mapped Configuration and Status Register (MMR) Interface" in tab "Controller\Configuration, Status and Error Handling" for External Memory Interfaces Intel Cyclone 10 FPGA IP...
NurAida_A_Intel
Frequent Contributor
Frequent ContributorHi Konst_777,
You can try to optimize the timing by change Quartus assignment -> setting -> compiler setting and select one of the performance option under Optimization mode then recompile design again. (refer to page 201 of the EMIF handbook for more details on how to optimize timing)
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20116.pdf
Hope this helps
Regards,
NAli1
