External Memory Interfaces Intel Cyclone 10 FPGA IP: MMR interface trouble

Dear sstrell,

Thank you very much for your desire to help me.

Actually the input "pll_ref_clk" is connected to "emif_refclk" (Clock Bridge Intel FPGA IP). This component is collapsed, but you can see the signal "emif_refclk_out_clk" in the column "Clock".

The project is already working, but the module is very hot and I wanted to switch DDR3 in the deep power-down mode at the time when image generation is not performed. That's why I want to use MMR register for control the deep power-down mode with sideband5/sideband10 addresses. But when I checked "Enable Memory-Mapped Configuration and Status Register (MMR) Interface" nothing inputs added to the "sodimm". And I don`t understand what I have to do in this situation?