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Altera_Forum's avatar
Altera_Forum
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13 years ago

EXT Function Error

I've used the following line of code in Xilinx with no issue, but now Quartus is flagging this as an error. The error is shown below.

--error

Error (10779): VHDL error at addr.vhd(609): expression is not constant

--code...

sum_azp_azpos_scale <= EXT( sum_azp_azpos_comp(15 downto (CONV_INTEGER(az_scale_fact1))), 16);

I'm using the following packages.

--packages

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.STD_LOGIC_MISC.ALL;

use IEEE.NUMERIC_BIT.ALL;

Any suggestions?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    yes, altera doesnt like non constant ranges. You'll have to use a select to slice the signal sum_azp_azpos_comp, and then extend it with the EXT function.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thanks!

    Could you please give me a quick example?

    The az_scale_fact1 is defined below.

    --code

    signal az_scale_fact1: std_logic_vector(2 downto 0);
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    assuming this is outside a process: 

    
with az_scale_fact1 select
  sum_azp_azpos_scale <=      sum_azp_azpos_comp(15 downto 0)       when "000",
                         EXT( sum_azp_azpos_comp(15 downto 1) , 16) when "001",
                         EXT( sum_azp_azpos_comp(15 downto 2) , 16) when "010",
  --etc

    can I ask why az_scale_fact1 is a std_logic_vector and not an integer?

    and also - Im going to be a code facist - any chance you want to come into the 1990's and use IEEE standard VHDL?