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Altera_Forum's avatar
Altera_Forum
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11 years ago

Export a listing of all used LEs

Hello everyone,

I have a customer that would like to get a listing of the location of each LE, DSP memory block in an FPGA design. I'm not exactly sure what they want to do with that, but if I understood correctly what they asked, I should generate a list with each node name and the corresponding location on the FPGA floor plan.

I had a look in the Quartus documentation to see if such a thing existed but didn't find anything quite like it. It looks like the netlist formats are mostly used after synthesis and before fitting, so won't include the location information. The Chip Planner doesn't seem to have any export function, and the technology map viewer can only export JPEGs, and I don't think they will include location information.

Do any of you have an idea? Would the only solution to write a tcl script to do that? Is there a way in tcl to loop in all available nodes and print out the corresponding location, or the other way round, to loop in all FPGA locations and print out the corresponding node name? I just hope it won't take all night to loop in the more-than-hundred-thousand locations...

Thanks a lot!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Don't the post fitting equations contain the wanted information? => Start Equation Writer (Post Fitting)

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    You can use the following back-annotation script. Just change the location_wildcards to {DSP*} and it will only write DSP locations. By default the variable debug is set to 1, so it will write the assignments to a file called ba_assignments.tcl rather than to the .qsf. (It's pretty self-documented and should be easy to use)

    http://www.alterawiki.com/wiki/back_annotation_script