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endmodule should not have a semicolon (;) at the end
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Thank you, really. (BTW: I think an empty instruction should be tolerated, and the error message could be more informative).
I have, however, more problems.
About line, containing '$finish', the compiler gives the warning "ignoring unsupported system task".
(As far as I know, $finish should be supported)
The bigger problem is the error the compiler reports:
"Can't synthetise current design -- Top partition does not contain any logic"
Which is absolutlely true. But, I did not want to synthetise, just to simulate and show the waveform.
Is there any setting that allows to to that?
And in general, shall I change some setting to compile ONLY for simulation?
Honored Contributor
