Expected ALTPLL behaviour

Ahhh. I would ignore it, or file a Service Request. If it's not in the timing report, then the Chip Editor must be doing something wrong, or displaying something different than what you expect. The timing report is what really should be used.

You should get the same type of analysis as you get in Xilinx. Note that for source-synchronous you're actually going to miss some uncertainty. For example, at the slow corner you get a worst case data and clock Tco. But on a given piece of silicon, one of the paths might be "less worst case" than the other. You won't see that in SII, and didn't see it in Xilinx. (It should be small, but it's real).

For all 65nm families and beyond(SIII, CIII, etc.), and using TimeQuest, the models have this type of information. So at a corner, say the slow corner, the paths have a fast On-Die Variation nad slow On-Die Variation value. So for a source synchronous output, TQ will use the slow verion for the data and the fast version for the clock going off chip, and vice versa for the external hold analysis. Also, rise/fall times and unateness come into affect, as well as common clock path pessimism removal. This doesn't help you with your current design, but is a plug of things in the newer family models that TimeQuest takes advantage of.