Expected ALTPLL behaviour

Where do you get 4.13ns from the path listed above? There should not be 4.13ns from the dedicated clock input port to the PLL input.

Also, as a hint, make sure you're looking at the big picture which, for I/O timing, is all based on clock ports and data ports. The delay from the clock port to the PLL input doesn't really matter by itself, but as a component of your clock port relationship to your data ports. What are you seeing for I/O timing across models? What is it you're trying to do with this number. In fact, the whole PLL compensation modes don't really matter without more info. If the input clock is perfectly aligned to the register clock, that doesn't matter if the delay to/from that internal register to the I/O port is 10ns. It's best to think of it at that system level(which you might be doing and have broken it down to the micro-parameter level), but I'm not sure what you're trying to do at the system level.