Expected ALTPLL behaviour

Rysc, Brad,

Many thanks again for your input here -

Rysc.....

I take your point about the PVT invariance of the PLL - it's exactly this behaviour that I want....except that, in this case, there appears to be a portion of the input delay which is not compensated. i.e. rather than align the input PIN of the device with the clock as seen at the destination register, "NORMAL" mode appears to align the input PORT of the PLL with the clock as seen at the destination register. So I really need to understand the nature of the 4.13ns pin --> PLL input delay. Since this is nominally dedicated PLL routing, perhaps the uncertainty is negligible. Certainly, when comparing "fast corner" and "slow corner" timing, it's the only figure which doesn't change.

I'd be very interested to read your document on source synchronous constraints, if you're happy to share it.

Brad.....

Good idea to analyse the register-to-register paths. Unfortunately, there aren't any - the PLL clocks some DDR input registers, and the first register-to-register path is cross-domain, back into an independent system clock. That said, the phase shift I'm using (for the purposes of trying to understand the PLL behaviour better) is zero, which should make the numbers straightforward to interpret.

Ultimately, I think it boils down to whether or not you believe (or rather how you interpret) the figure I've attached from the device handbook. This shows the "PLL Reference Clock at the Input Pin" aligned with the "PLL Clock at the Register Clock Port". To me, that implies compensation of the COMPLETE clock path, from the input pin, to the target register - but I'm not seeing that reflected in the chip planner or in timing analysis figures.

Cheers.

file:///C:/DOCUME%7E1/Declan/LOCALS%7E1/Temp/moz-screenshot-2.jpg file:///C:/DOCUME%7E1/Declan/LOCALS%7E1/Temp/moz-screenshot-3.jpg