Expected ALTPLL behaviour

Note that you can't really do a source synchronous interface with TAN. (Though many people have, but you're basically writing down the clock's Tco and then comparing the other Tcos to it.) TimeQuest allows you to constrain data outputs in relationship to clock outputs.

I haven't looked specifically at input port -> PLL input delays over various models. Technically, I think they should change. That being said, the overall clock delay shouldn't change much, as that's one of the main features of a PLL, in that it's PVT invariant, i.e. as your global clock trees vary over PVT, the PLL compensates by the inverse amount, making the total delay relatively constant. Also, if it's the source synchronous side, the clock delay should pretty much cancel out since that delay feeds both the data and clock outputs. I have a document I wrote on constraining source synchronous interfaces, if you're interested(if you have a good handle, it's probably not worth wading through another one...)