Expected ALTPLL behaviour

I have been looking at TimeQuest over the last few weeks - mainly because some of the Altera guidelines on constraining source synchronous interfaces are written specifically for it......could yet make the switch.

To answer your question, yes, feedback_clk_in is the name of the clock port. I'm not using external feedback for the PLL, just creating it in NORMAL mode, which should nominally compensate for delays on the input clock path.

But, it seems, the PLL does not compensate for the delay I see between the device input pin and the PLL input port. So I guess my next question is, what is the nature of that delay? I guess there are two reasons for using a PLL on this path. 1. To deskew/remove the input clock delays and reduce uncertainty in the static timing analysis for that part of the interface. 2. To potentially add a phase shift for ease of resynchronisation.

I'm primarily concerned with static timing uncertainties at the moment - I have noticed that the input delay (from pin to PLL input) remains totally fixed at 4.13ns for this path regardless of whether I run "fast corner" or "slow corner" timing - so does it seem reasonable to conclude that there is minimal uncertainty (over PVT) with regards to this delay i.e. I need build no margin into the static timing to account for it? That conclusion makes me a bit nervous, but maybe it's the correct assumption......?