Expected ALTPLL behaviour

Rysc,

Many thanks for your reply - very much appreciated.

As far as I can see, the correct dedicated PLL input is being used here. The target device is a Stratix II GX: EP2SGX90EF1152. The PLL is created in NORMAL mode, and connected to pin AN19 (clk4p) of the device. Under Fitter/Resource Section/PLL Summary the tool is reporting that the PLL_Location is "PLL12" and the Inclk0 signal type is "Dedicated Pin". There are no relevant warnings/critical warnings in the output**.

From the Stratix II GX device handbook, Vol.2, Page 7-13, Table 7-7, it seems that the chosen clock input is a valid dedicated input for PLL_12. So I'm still at a loss as to why the input does not seem to be properly compensated. A chip planner screenshot (which I will try to attach) suggests the pin and PLL are indeed adjacent, but reports the big delay.

Ultimately I'm also interested in source synchronous operation - in fact what I'm trying to do is a static timing analysis of a memory interface (for which I think source synchronous operation may be a better mode). I see an identical delay from the input pin when I try the same design with a source synchronous PLL - and the compensation figures, though different, do not tie up any better with the expected behaviour from the datasheet.

Given that I'm trying to be precise in analysing the timing uncertainties of the interface concerned, I really need to be sure that the delays I see in Quartus are correct. If the basic mode of operation of this PLL does not tie up with the datasheet (at least to within a believable delta, if not 0, like you say) I'm reluctant to conclude that everything is believable.

Cheers,

D.

**One warning which I DO see is the following:

Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled

....However, enabling clock latency analysis in the settings (whilst it gets rid of this warning) does not change any of the reported numbers.