Expected ALTPLL behaviour

Why is your input pin to PLL 4.130ns? I'm guessing you're not using the PLL next to the dedicated clock pin, which will cause a long route that can't be compensated for(I think there's a warning amongst the thousand other warnings.) In simplistic tems, a PLL has two inputs, your clock and feedback clock, and will phase shift it's output until the feedback clock aligns with the input clock. Also, the output goes on a balanced, low-skew clock tree, and tries to hit all the destination registers at the same time. On one of those equally timed branches of the tree though, rather than feed a register's clock, it feeds the feedback port of the PLL.

Now, that's the simplistic version. Besides changing the feedback path, I think there's some stuff that do to help get the other modes(like source-sync mode). But a mode like that won't be too far off from normal mode.

Anyway, when you do a report_timing -detail full_path, you should see good details, but that path from the input pin to a PLL that's far away can't be compensated for, and that's why your offset doesn't equal the full clock delay. (Even when it does feed the right PLL, they don't add up to 0 or anything like that, but they get a lot closer.)