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dsun01's avatar
dsun01
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4 years ago
Solved

exec elab_debug error

Dear Support,

I have a project from Texas Instruments. I am learning how to port it to Intel A10 GX development board. I use Quartus Pro 21.3 Generate Simulator Setup Script created a TCL. and it runs all the want to one error.

# [exec] elab_debug
# vsim -voptargs="+acc" -pli "C:/intelfpga_pro/21.3/quartus//bin64/sld_sysconsim.dll" -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L .......................... fx3_clkctrl -L fx3_iopll -L loopback_fifo ed_sim.ed_sim
# Start time: 14:46:48 on Nov 28,2021
# ** Error (suppressible): (vsim-19) Failed to access library 'ed_sim' at "ed_sim".
# No such file or directory. (errno = ENOENT)
# Error loading design
# End time: 14:46:53 on Nov 28,2021, Elapsed time: 0:00:05
# Errors: 1, Warnings: 0

I use .................... represent a very long list.

I attached the msim_setup.tcl file in zip format.

I didn't expect Quartus can generate a functional testbench for me. but I do relay on it to create a working simulation structure.

what should I do to make the ld_debug complete successfully?

I need a dummy top level testbench that I can fill in test contents. I can make one, but I don't know how to tell/edit the .tcl file in include it in.

Best Regards,

David

  • IntelSupport's avatar
    IntelSupport
    4 years ago

    Hi David,


    Thanks for the project file. I will try to replicate the issue and update to you.


    Regards,

    Pavee


6 Replies

  • dsun01's avatar
    dsun01
    Icon for Contributor rankContributor
    4 years ago

    Dear Support,

    In the msim_setup.tcl in the last post. there are few places I don't understand.

    1. the TCL assigne loopback_fifo as the top_level_name. I don't understand why, loopback_fifo is just one the IP used in the system, not top testbench. can I change it to the real top level testbench.?

    if ![info exists TOP_LEVEL_NAME] {
    set TOP_LEVEL_NAME "loopback_fifo.loopback_fifo"
    }

    2. how do I add the testbench_top.v to the .tcl where should I put the testbench_top.v file so the .tcl will find it.

    thanks,

    David

  • IntelSupport's avatar
    IntelSupport
    Icon for Contributor rankContributor
    4 years ago

    Hi David,


    Please allow me some time to reproduce the error

    and will be back with updates. Thanks


    Regards,

    Pavee


    • dsun01's avatar
      dsun01
      Icon for Contributor rankContributor
      4 years ago

      Hi Pavee,

      I understand it is very detail and time consuming, appreciate your help, I attached the whole project here just in case. It was originally a TI demo project. I am working on port it to Intel A10 GX dev Kit. so it is different chip on a different board and upgrade from Quartus 16 to 21.3.

      I hope I can create a system level simulation environment and seems Quartus has this feature. I used to create a Modelsim project, add all related .v files. but the latest design methodology make this approach very hard, because the Platform Designer generate so many related files and they are scattered in some many different directory.

      So the function call "Generate Simulator setup script for IP" is very critical and attractive. for all IP level modules it works fine. for example, the Intel emif example project will generate a top level testbench called ed_sim.ed_sim.

      I think I need create this testbench by myself(Quartus has a Start Test Bench Template Writer). but I don't know how to include it to the .tcl. I need help/instruction/tutorial to add my system level testbench in the .tcl file.

      for the project attached. there is a conflict while compiling. if enable "generate IP simulation model when generating IP", then the "analysys &Synthesis" has error.

      if you disable the "generate IP simulation model when generating IP", then when you run "Generate Simulator setup script for IP", there will be a lot of error, So I have to keep toggling this generate IP simulation feature between simulation and synthesis. but this is not a critical issue.

      Thank you for help.

      David

  • IntelSupport's avatar
    IntelSupport
    Icon for Contributor rankContributor
    4 years ago

    Hi David,


    Thanks for the project file. I will try to replicate the issue and update to you.


    Regards,

    Pavee


    • dsun01's avatar
      dsun01
      Icon for Contributor rankContributor
      4 years ago

      Hi Pavee,

      After few days patient learning, I think I figure out my problem. in fact, it is nothing. just need to read the tools guild and manual carefully.

      I write few more sentence here, just in case anyone have the same question.

      to create your first Modelsim project, if you have something unclear. you need read this document carefully. if you understand what it says, you should be able to do your job.

      ModelSim - Intel FPGA Edition Simulation Quick-Start: Intel Quartus Prime Pro Edition

      Thank you for your help,

      David

  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    4 years ago

    I'm glad that the error has been resolved, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you