Forum Discussion
New Contributorexample transfer 50mhz to hz
New Contributormaybe we have wrong idea.
my idea is i want to understand the code in the always @ (posedge CLOCK_50) begin.
For example i wrote this code
module Convert(CLOCK_50);
input CLOCK_50;
reg [ 25: 0 ] Q;
reg CLOCK = 0;
always @ (posedge CLOCK_50) begin
if (Q == 25000000 ) begin
Q <= 0;
CLOCK = !CLOCK ;
end
else
Q <= QQ + 1;
end
So i have reg [25:0] Q. is this Q is 25 bit???
if(Q==25000000) // is if Q == 25bit then the CLOCK = 1 hz? or 1mhz ? i dont know .
This main question i have to understand in this alway @(posedge clock_50) begin clock_50 = 50mhz.
i want to understand how the code work in here. if i want to get 50000000/9000 = 5555.5 or 5556
so if i want to get 9000 then i ran
If(Q==5556)
Q<=0
CLOCK <=1; // this is now clock == 9000hz?
Regular ContributorFirst a reg [25:0] value is a 26 bit binary number, and can have a value between 0 and 2^26-1, or 67,108,863.
@(posedge clock_50) is going to toggle every 20ns (assuming a 50MHz clock input). So each count will be 20ns.
5556 * 20ns will be 111.12usec, or 8999.28 KHz.
Do you have access to a graphical verilog simulator as part of your Quartus install? That may make it easier for you to understand.
