New Contributor
New ContributorThank you, Wincent. The device I am using is:AGIB041R31B1I2VC. I generated a example design with gen3 1x16 . Having passed the analysis & synthesis, but unable to pass the jitter, is it necessary to reallocate clock and data pins ?
Regular ContributorHi Geats,
I am able to compile 100 % on Gen3 1x16 in Agilex F-series device.
For your device, You may need to do the pin placement accordingly based on your device OPN.
Because our design's example pin placement is only targeted F-series devkit
Detail about the pin placement you may refer to
Or you may refer to the design .qar in the attachment (for F-series) under .qsf file
You may re-use more then 60-80 % of the pin information.
Regards,
Wincent_Altera
p/s: If any answer from the community or Altera Support is helpful, please feel free to give the best answer or rate 9/10 survey.
New ContributorWith the example design of F-series devkit based on your suggestion has passed the compilation. Thank you, Wincent
Regular ContributorHi Geats,
Glad that my suggestion is able to help you. Do you have any further question ?
Else do I have your permission to close this ticket ?
Regards,
Wincent
New ContributorI also want to ask if I can use PCIe IP alone to generate Gen3x1 mode and only connect to refclk0 in this situation? Or can I use a buffer to connect a reference clock to both refclk0 and refclk1? Does this buffer require a specific IP core? Or simply generate it by user logic？
