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Altera_Forum
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12 years ago

Errorr simulating in Quartus (Zero-time oscillation in node)

Errorr simulating in Quartus (Zero-time oscillation in node) Hello everybody. I'm doing block control cache for study project and I have some problems when I use a functional simulation. Proc...
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Altera_Forum
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12 years ago

A logic loop is when X = f(A,X), ie. the output is a function of itself. So I assume you have generated a couple here.

Is there any reason you have not created a synchronous circuit?