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Shwetha_G_S's avatar
Shwetha_G_S
Icon for New Contributor rankNew Contributor
3 years ago

Error:Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints 2 pins

We use "10AS048E3F29I2SG" device, and in our hw design,FPGA uses shared I/O as following: FPGA_RTC_FAN_SENSOR_SDA @D20 (SHARED_Q1_5) FPGA_RTC_FAN_SENSOR_SCL @E20 (SHARED_Q1_6) We are tryi...
aikeu's avatar
aikeu
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Shwetha_G_S,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Thanks.

Regards,

Aik Eu


  • Shwetha_G_S's avatar
    Shwetha_G_S
    Icon for New Contributor rankNew Contributor
    3 years ago

    In addition to the problem mentioned earlier, one more thing is there,

    In the same design, by mistake LVDS signals (these will be used for 1G Ethernet Ports) are connected on those pins where Soft-CDR support is not there. Is there any solution for the same that LVDS signals can support non soft CDR mode pins ?

    Kindly give a solution for this.