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Altera_Forum's avatar
Altera_Forum
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13 years ago

Error

I vonder what is wrong in this code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.ALL; entity uppgift_vhdl_3a is port ( Sys_clk,...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Ahh, didn't notice what you were missing - add

end rtl;

at the end. You need to close out your architecture.