Altera_Forum
Honored Contributor
13 years agoerror with using a macro
Hello,
Example with a_74283. LIBRARY altera; USE altera.maxplus2.all; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY macro_eg IS PORT ( num_a :IN STD_LOGIC_VECTOR (4 DOWNTO 1); num_b :IN STD_LOGIC_VECTOR (4 DOWNTO 1); carry_in :IN STD_LOGIC; carry_out :OUT STD_LOGIC; sum_out :OUT STD_LOGIC_VECTOR (4 DOWNTO 1) ); END macro_eg; ARCHITECTURE adder OF macro_eg IS COMPONENT a_74283 PORT ( a :IN STD_LOGIC_VECTOR (4 DOWNTO 1); b :IN STD_LOGIC_VECTOR (4 DOWNTO 1); cin :IN STD_LOGIC; cout :OUT STD_LOGIC; sum :OUT STD_LOGIC_VECTOR (4 DOWNTO 1) ); END COMPONENT; BEGIN add1 : a_74283 PORT MAP (a => num_a, b => num_b, cin => carry_in, cout => carry_out, sum => sum_out); END; but I get, Error: Node instance add1 instantiates undefined entity a_74283 . I have the same problem with using a User Defined macro (I just include/add the folder of the VHDL program that is going to be used as the macro in the User Libraries). I have no problem/errors using macros in AHDL (using the INCLUDE keyword). Thank you