I am trying to teach myself FPLDs in AHDL, VHDL and Verilog.
The Technikon I attended added an FPLD course (in Graphic Design Entry, AHDL & VHDL) after I graduated, so I bought the kit from the lecturer (a while back). I have only recently started with it. The FPLD (EPM7032SLC44-10) is also obsolete. But because I am working from course notes and MAX+plus II is still available, I am using it as a beginner.
Back to the problem:
I also get the error for using a user macro/component. I use a previous exercise as a component; I add the folder of the exercise (component to use) in User Libraries. Following is the program (exercise) using exercise 1v as a component:
-- Exercise 14v: A 4-Bit Up Counter Using a Macro as the 7-Segment Display Decoder
ENTITY Ex14v IS
PORT
(
clk :IN BIT;
SSout :OUT INTEGER RANGE 127 DOWNTO 0
);
END Ex14v;
ARCHITECTURE usermacro OF Ex14v IS
SIGNAL cnt :INTEGER RANGE 15 DOWNTO 0;
COMPONENT ex1v IS
PORT
(
bn :IN INTEGER RANGE 15 DOWNTO 0;
SS :OUT INTEGER RANGE 127 DOWNTO 0
);
END COMPONENT;
BEGIN
PROCESS
BEGIN
WAIT UNTIL clk'EVENT AND clk = '1';
cnt <= cnt + 1;
END PROCESS;
decoder :ex1v PORT MAP (cnt,SSout);
END;
Following is exercise 1v program:
-- Exercise 1v: A 4-Bit Binary to 7-Segment Decoder
ENTITY Ex1v IS
PORT (
bn :IN INTEGER RANGE 15 DOWNTO 0;
SS :OUT INTEGER RANGE 127 DOWNTO 0
);
END Ex1v;
ARCHITECTURE max OF Ex1v IS
BEGIN
SS <= 2#111_1110# WHEN bn = 0 ELSE -- Binary, Decimal
2#011_0000# WHEN bn = 1 ELSE
2#110_1101# WHEN bn = 2 ELSE
2#111_1001# WHEN bn = 3 ELSE
2#011_0011# WHEN bn = 4 ELSE
2#101_1011# WHEN bn = 5 ELSE
2#101_1111# WHEN bn = 6 ELSE
2#111_0000# WHEN bn = 7 ELSE
2#111_1111# WHEN bn = 8 ELSE
2#111_1011# WHEN bn = 9 ELSE
2#111_0111# WHEN bn = 10 ELSE
2#001_1111# WHEN bn = 11 ELSE
2#100_1110# WHEN bn = 16#C# ELSE -- Binary, Hexadecimal
2#011_1101# WHEN bn = 16#D# ELSE
2#100_1111# WHEN bn = 16#E# ELSE
2#100_0111# WHEN bn = 16#F#;
END;
Adding the folder: Options -> User Libraries... -> ..\ex1v (folder containing exercise 1v files) -> Add -> OK