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Altera_Forum's avatar
Altera_Forum
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10 years ago

Error while executing: Force

Hello all, I recently installed ModelSim, and am having all sorts of issues with it. I am trying to simulate a project that contains several Altera IP cores (counter, ROM, PLL, ALTDIDO) and am ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

So, I've cleaned out anything that was VHDL in the project, including some old vhdl.do files. Additionally, I renamed anything in the path of the project/simulation that had spaces in the directory name. Now, it appears there are no errors on startup of ModelSim. However, if I select "simulate" on one of the IP cores in my design, I get the following: 

ModelSim> vsim work.TX_PLL_altpll
#  vsim work.TX_PLL_altpll 
#  Start time: 16:40:32 on Feb 22,2016
#  ** Error: Failure to obtain a Verilog simulation license. Unable to checkout any of these license features: alteramtivsim or alteramtivlog.
#  Error loading design
#  End time: 16:40:32 on Feb 22,2016, Elapsed time: 0:00:00
#  Errors: 0, Warnings: 0

Do you still think this is a VHDL error? Is there any way I can find the offending vhdl file so I can remove it?