RDoev1
New Contributor
5 years agoError when Importing HDL to Create Components in Platform Designer
The attached screenshots show errors received when trying to import HDL to create an AXI4Lite slave Generic Component in Platform Designer. Following the Intel Video for "Importing HDL to create Qsys Pro Components", the process seemed applicable even though the example from the video pertained to an Avalon MM slave component. So, after separating the imported signals into conduit, clock sink, and reset sink I received 3 errors shown in the first screenshot mentioning that a clock and reset interface must be assigned to the axi4l interface. After assigning the clock sink and reset sink in the parameter of the axi4l interface, I received 5 errors. It appears I am fundamentally missing an aspect of this feature. Any thoughts? Thanks, Roy