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I'm presuming you have generated the system in Platform Designer or performed at least synthesis to have the system design files generated.
Also, you mention ModelSim. Are you using ModelSim-Intel FPGA edition or stand-alone ModelSim (SE or PE)? If you are using stand-alone ModelSim, you have to set up the IP simulation models to get compiled in the tool. The Intel edition has all this pre-compiled.
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Hello and thank you for the reply.
I have generated the VHDL using platform designer as well as synthesized the complete design with Quartus. I have also generated the simulation libraries. I am aware of the pre-compiled libraries in Modellsim-Intel FPGA edition, but I do not believe this to be an issue related to those as I have attempted this simulation using ModelSim-Intel FPGA edition, ModelSim PE and Questa Prime. All three simulation packages give the same error.
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