Honored Contributorwe have problem in compiling VHDL code in Quartus II software. Every time we compile it shows the Error:top level design entity " file name" is undefined.
We are even taking care of the case sensitivity. Our file name, new created project name and entity name in the code are all same. Plz help us regarding this.
Honored ContributorHello everybody from rainy southern Germany,
I had the same issue, and the tool gives you no sort of description what is wrong, I was missing my HDL file - it was not defined. As posted below, just check under Project - Add/Remove files in project. If you see no files listed then that is the problem. By the way, changing the severity of the error messages for HDL input to level 3 did not give me any additional info. This could be improved in my opinion. :confused: Cheers, EricHonored ContributorI encountered exactly the same problem. I verified Assignment->Settings (with my project name)->General/Files/Device and everything looked fine. I also did Project->Add/Remove Files in Project... and everything looked normal. I had a very simple schematic file under the same directory with the project file (directory and project file have the same name). I wanted to try out with the simple one first since do not want to spend time on the complete project before I know it would work. I used the New Project Wizard and went over their tutorial several times. Can anybody explain to me more since I am at dead end. I am new to Altera and this is the free version with Cyclone II. I also tried to call Altera Tech Support but got the recorder taking me around the loop. Thank a bunch.
SMLHonored ContributorHonored ContributorHow do I post my project into the forum. GPK please show how. Thank you.
Regards, SMLHonored ContributorMake a Quartus archive (*.qar file) from the project, go the manage attachments zone when writing a reply.
Honored ContributorI was not able to get any *.qar file. The message I got after archiving was:
"Project archiving created; however, Analysis Elaboration was not successful. As a result, some files could not be archived". None of the output files complied with the attachment format; therefore I could not upload any files for you to examine. Any ideas please. Regards, SMLHonored ContributorHonored ContributorThank you a lot you guys. I sincerely welcome as much help as I can get. Here is the zip file.
Regards, SMLHonored ContributorI see that your project is set to a top level entity "DramControl", but there's no file with this name. The bdf file apparently intended as top level is "DramCltGen.bdf". It can't work this way.
If you open DramCltGen.bdf, you can set it as top level entity in the project menu. As the next problem, DramCltGen.bdf has illegal pin names containing a "#". There are additional logic errors and possible problems in the design, e.g. an internal tris-state buffer that is causing an 'U' unknown logic state, when disabled. P.S. Regarding: --- Quote Start --- I was not able to get any *.qar file. --- Quote End --- I believe, that you get an error message, but a valid *.qar file has been generated and is contained in your *.zip file anyway.Honored ContributorThank a million FvM.
Regards, SML
