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Altera_Forum's avatar
Altera_Forum
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17 years ago

Error: top level design entity " " is undefined

we have problem in compiling VHDL code in Quartus II software. Every time we compile it shows the Error:top level design entity " file name" is undefined. We are even taking care of the case se...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I solved this in Quartus II 11.0 by going Assignments > Settings > General and making my Top-level entity the name of my top level Verilog module (not its filename).

e.g. for a file named example.v

module circuit (output f, input x,y,z);

assign f=(x|(y&~z))&~(y&z);

endmodule

make the Top-level entity "circuit" not "example"