Error: top level design entity " " is undefined

I think this relates to th OPs problem. There seems to be a typo in the supplied file from Altera as part of DE2_tutorials\design_files data set has the top level entity/arch named addersubtractor2 in addersubtractor.vhd, it should of course be addersubtractor the file is marked (C) 2005 Altera Corporation.

as shown here:

-- Top-level module

ENTITY addersubtractor2 IS

GENERIC ( n : INTEGER := 16 ) ;

PORT ( A, B : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;

Clock, Reset, Sel, AddSub : IN STD_LOGIC ;

Z : BUFFER STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;

Overflow: OUT STD_LOGIC ) ;

END addersubtractor2 ;

ARCHITECTURE Behavior OF addersubtractor2 IS.....

This section of the file should read (as it did in 8.0sp1 supplied files):

-- Top-level module

ENTITY addersubtractor IS

GENERIC ( n : INTEGER := 16 ) ;

PORT ( A, B : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;

Clock, Reset, Sel, AddSub : IN STD_LOGIC ;

Z : BUFFER STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;

Overflow: OUT STD_LOGIC ) ;

END addersubtractor ;

ARCHITECTURE Behavior OF addersubtractor IS.....

This file is marked -- (C) 2004 Altera Corporation. All rights reserved.

Looks like a typo possibly, but if you change the top level entity and architecture to match as shown it will compile ok. Not helpful for beginners!