Error: The pin "data[5]" has multiple drivers due to the constant driver

Hello,

Im kinda new with Quartus II and VHDL so let's go.

Im projecting a simple CPU. with 4 registers. so i have 2 signals to let the register (normal_buffer) read from the bus or right. those signals are Rin and Rout.

i made a MUX to select who is reading or writing on the given state.

When i trie to compile i get the error "Error: The pin "data[5]" has multiple drivers due to the constant driver"

this error happens when i do this

" sel_code_rout <= "110"; "

what this error means? what im doing wrong?

thank you very much

Observation: Please ignore the coments that are not in english. =D

library ieee;
use ieee.std_logic_1164.all;
LIBRARY CPU;
USE CPU.ula_package.all;
ENTITY CPU IS
 
 port( input: in std_logic_vector(7 downto 0);
    clock: in std_logic;
    reset : in std_logic;
    data: INOUT std_logic_vector(7 downto 0);
    output: out std_logic_vector(7 downto 0)
    );
END CPU;
ARCHITECTURE test of CPU is
 
type state is (A,B,C,D);
 
signal s : state;
signal Rin,Rout : std_logic_vector(0 to 6);
signal r1,r2,r3,r4,Y,Z,RI: std_logic_vector(7 downto 0);
signal zero: std_logic;
signal control: std_logic_vector(1 downto 0);
signal sel_code_Rin,sel_code_Rout,sel: std_logic_vector(0 to 2);
 
signal conta : std_logic_vector(7 downto 0);
signal i : std_logic;
 
begin
 
 
P_C : PC port map(data,i);
 
reg1: normal_buffer port map(data,Rin(0),Clock,r1);
reg2: normal_buffer port map(data,Rin(1),Clock,r2);
reg3: normal_buffer port map(data,Rin(2),Clock,r3);
reg4: normal_buffer port map(data,Rin(3),Clock,r4);
reg_Y: normal_buffer port map(data,Rin(4),Clock,Y);
reg_RI: normal_buffer port map(data,Rin(5),Clock,RI);
 
tri_state_1: tri_buffer port map(r1,Rout(0),data);
tri_state_2: tri_buffer port map(r2,Rout(1),data);
tri_state_3: tri_buffer port map(r3,Rout(2),data);
tri_state_4: tri_buffer port map(r4,Rout(3),data);
tri_state_Y: tri_buffer port map(Y,Rout(4),data);
tri_state_RI: tri_buffer port map(RI,Rout(5),data);
 
 
 
--LIGACAO FEITA. FAZER AS CONTAS!
unidade_logica: ULA port map(Y,data,control,zero,conta);
reg_Z: normal_buffer port map(conta,Rin(6),clock,Z);
tri_state_Z: tri_buffer port map(Z,Rout(6),data);
 
--seleciona qual registador vai escrever no barramento
with sel_code_Rin select
Rin <=
 "1000000" when "000", --R1
 "0100000" when "001", -- R2
 "0010000" when "010", -- R3
 "0001000" when "011", --R4
 "0000100" when "100", --Y
 "0000010" when "101", --RI
 "0000001" when "110", -- Z
 "0000000" when others;
 
 
-- seleciona qual registrador vai receber dados do barramento
 
with sel_code_Rout select
Rout <=
 "1000000" when "000", --R1
 "0100000" when "001", -- R2
 "0010000" when "010", -- R3
 "0001000" when "011",--R4
 "0000100" when "100", --Y
 "0000010" when "101", --RI
 "0000001" when "110", -- Z
 "0000000" when others;
 
 
 
 
 
 
process (data,reset,clock)
 begin
 
  if reset = '0' then
   s <= a;
 
 
 
 
  elsif (clock'event and clock = '1')  then
 
 
 
 
    case s is
 
     when A =>
 
      sel_code_Rin <= "101";
      i <= '1';
      output <= "00000001";
      s <= B;
 
     when B =>
      --sel_code_rin <= "111";
      i <= '0';
 
      case RI(7 downto 5) is
 
       when "000" =>
        output <= "00000000";
       when "001" =>
        output <= "10000001";
         s <= C;
       when "010" =>
        output <= "00000010";
       when "011" =>
        output <= "00000011";
       when "101" =>
        output <= "00000101";
       when "100" =>
        output <= "00000100";
 
       when others =>
        output <= "00000111";
 
 
 
      end case;
 
     when C =>
 
      --FAZER RIN E ROUT!
 
      sel_code_rin <=  "100";
      sel_code_rout <= "110"; <= WHEN I DO THIS I GOT THE COMPILER ERROR!
 
 
 
 
      s <= D;
 
     when D =>
 
      control <= "00";
 
 
 
 
     when others =>
      output <= "11111111";
 
      --sel_code_rout <= "111";
 
      s<= A;
 
    end case;
 
 
 
 
 
  end if;
 
 
 
 end process;
 
 
 
 
 
 
 
 
 
 
end test;