Forum Discussion
Altera_Forum
Honored Contributor
15 years agoI don't think they are using my data port at the same time.
take a look Here is my tri-state bufferLIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
ENTITY tri_buffer IS
PORT(
my_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
sel : IN STD_LOGIC;
my_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END tri_buffer;
ARCHITECTURE maxpld OF tri_buffer IS
BEGIN
with sel select
my_out <=
my_in when '1',
(others => 'Z') when others;
END maxpld;
Here is my buffer library ieee;
use ieee.std_logic_1164.all;
entity normal_buffer is
port(input: in std_logic_vector(7 downto 0);
canWrite : in std_logic;
clock : in std_logic;
output: out std_logic_vector(7 downto 0));
end normal_buffer;
architecture logic of normal_buffer is
begin
process
begin
wait until clock'event and clock = '1';
if canWrite = '1' then
output <= input;
end if;
end process;
end logic; and my PC! library ieee;
use ieee.std_logic_1164.all;
entity PC is
port(output : out std_logic_vector(7 downto 0);
i :in std_logic
);
end PC;
architecture logic of PC is
--signal code : std_logic_vector(7 downto 0);
begin
process(i)
begin
if i = '1' then
output <= "00100000";
end if;
end process;
end logic;