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Altera_Forum's avatar
Altera_Forum
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8 years ago

Error simulating the waveform

Hi guys, I've been trying to simulate a VHDL code in Quartus II, but every time I tryed, I got the messages (it is in cap2 file). Anyone knows what these errors means?. Just another thing, when ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

1.Are you using any other file or test bench along with the code you posted?

There is no error in code i have tried in using Model-sim 10.5b, And i can't see extra bit created during simulation.

Best Regards,

Anand Raj Shankar

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